Lead Engineer – Hardware Offload (C/C++ / SR-IOV / DPDK)
Job Description
The OperAxis team is seeking a Lead Engineer – Hardware Offload for a leading technology company. This is a remote contract role on a team that pushes the performance limits of ARM-based bare-metal and superchip server platforms, moving networking and data-movement work off the CPU and into hardware. The ideal candidate is an expert C/C++ systems engineer who has tuned bare-metal performance end to end, from PCIe bus behavior and DMA paths to kernel-bypass networking. You'll implement and optimize hardware network offload, integrate and benchmark high-speed CPU-to-CPU interconnects, and improve both kernel and user-space code. Requirements • Proven experience with hardware offload and systems performance tuning • Hands-on expertise with SR-IOV, NFV and PCIe pass-through (VFIO) • Expert-level C/C++ for bare-metal performance work • Experience with high-speed CPU-to-CPU interconnects • Kernel-bypass experience: DPDK, eBPF/XDP and DMA driver development • Experience with ARM bare-metal and superchip platforms • Nice to have: SmartNIC/DPU, RDMA and virtio experience • BS/MS in Computer Science, Computer Engineering, Electrical Engineering, Mathematics or a related field
Responsibilities
- Implement and optimize hardware network offload (SR-IOV, NFV) on ARM bare-metal hosts
- Integrate and benchmark high-speed CPU-to-CPU interconnects
- Profile PCIe throughput, latency and bus bottlenecks
- Develop kernel-bypass data paths with DPDK, eBPF/XDP and DMA drivers
- Enhance kernel and user-space code for performance
- Configure PCIe pass-through and VFIO for virtualized workloads
- Evaluate SmartNIC/DPU and RDMA capabilities for offload
- Document benchmark results and lead performance tuning across the stack